As is well known, low power consumption BiCMOS processes provide for the formation, e.g., in logic circuits or memory devices, of protection structures against electrostatic discharges.
Such structures are commonly known as ESD protectors and are arranged to be active only in a particular condition, known as "snap-back", of the parasitic bipolar. This bipolar is a lateral npn transistor with field oxide (field oxide bipolar), which may undergo a breakdown from the collector terminal toward the substrate when the base-emitter junction is forward biased.
The parasitic lateral npn bipolar is commonly used, in CMOS processes with 0.5 .mu.m technology, as a protector, since it is a parasitic component inherent to the process and its provision does not add to the cost. This transistor is biased with the base-substrate to ground, and does not interfere with proper operation of the devices; in addition, it has ESD fail limits inherently higher than 5 kV, compared to the 2 kV usually provided by the specifications.
This is definitely so where the starting substrate is P-doped silicon having a high resistivity of about ten ohms per centimeter and a much larger thickness than the dimensions of the components integrated in the substrate. For example, the wafer of semiconductor material may exit the process with a thickness of about 300 .mu.m.
In this field of application, there is a demand for starting substrates of ever lower resistivity, even three orders of magnitude below the above-specified value. As illustrated in FIG. 3, an EPI epitaxial layer is grown over said semiconductor substrate whose resistivity exceeds that of the substrate and is about ten Ohms per centimeter, that is, same as that of the aforementioned P substrates.
This constructional expedient has been adopted to meet the requirement for immunity to the well known latch-up phenomenon that recurs more frequently with the scaling of the lateral dimensions of electronic components fabricated with BiCMOS processes.
The expanding use of low resistivity substrates overlaid with an epitaxial layer results in diminished strength of the devices to electrostatic discharges. This diminished strength affects both lateral bipolar transistors with field oxide and MOS transistors which utilize the npn bipolar as parasitic.
A marked reduction has been observed in the base resistances, for a given circuit structure. This deterioration of the base resistances has been ascertained experimentally.
For example, stressing tests carried out by the Applicant have shown that lateral npn bipolar transistors realized on semiconductor wafers having EPI epitaxial layers of different thicknesses undergo deterioration of the ESD protection when the thickness of the epitaxial layer is increased.
The appended FIG. 1 shows the results of these tests in the form of voltage vs. current plots at different thicknesses of the epitaxial layer. Performance begins to deteriorate as the EPI epitaxial layer is grown to 7 or 4 micrometers.
FIG. 2 is a voltage vs. current plot of the respective static characteristics of a lateral bipolar transistor with field oxide realized in substrates having epitaxial layers of different thicknesses.
It can be seen from this graph that the level of the trigger current increases as the thickness of the epitaxial layer decreases. The increase in current is due to that an increased number of holes injected into the low-resistivity substrate make the triggering of the bipolar snap-back phenomenon less likely to occur.
In fact, at small values of base resistance, high current levels become necessary to turn on the bipolar. On the occurrence of a large current discharge ESD), the electrons being injected from the emitter-base junction reach as far as the collector junction, and contribute the injection of additional holes into the base. This phenomenon attains a condition of equilibrium where the characteristic curve of the bipolar becomes near-linear.
The resistance along this linear segment of the characteristic is known as the "protector dynamic resistance Rd", and is dependent on the series resistances of the collector and the emitter, as well as on a smooth power-on of the structure.
A low Rd is essential to good ESD performance.
The stressing tests show that during the power-on transient, the circuit structure has a protector dynamic resistance Rd which increases inversely with the thickness of the EPI epitaxial layer. A most likely postulation is that the structure is affected by a non-smooth power-on, and this may be a major cause of the deterioration found when the structure is subjected to ESD stressing.
In all events, a current trend in the technology favors a progressive reduction of the parameters that govern the latch-up phenomenon. Thus, today's trend is toward reduced thickness of the EPI epitaxial layers, thereby exposing the electronic components to increased ESD risks.